1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and particularly to a NOR type electrically Flash erasable and programmable read-only-memory (Flash EPROM) for extracting charges from a floating gate to a diffusion layer in a memory cell.
2. Description of the Related Art
A basic element structure of a conventional Flash EPROM is a MOS type field effect transistor having two layer gates, in which a tunnel insulating film 1106, a floating gate 1102, an insulating film 1107, and a control gate 1103 are laminated in this order on a semiconductor substrate 1101, as shown in FIG. 1. In a program operation, electrons are caused to flow through the channel by applying a high voltage to a drain region 1104 and the control gate 1103 and connecting a source region 1105 to the ground. A program operation is executed by injecting the hot electrons generated by accelerating electrons in a high field near the drain region 1104 to the floating gate 1102. In an erase operation, the control gate 1103 is grounded and a high voltage is applied to the source region 1105, thereby applying a high voltage to a thin silicon oxide film 1106 (tunnel oxide film) between the floating gate 1102 and the source region 1105, so that Fowler-Nordheim tunneling current (FN current) is caused to flow. An erase operation is executed by extracting the electrons injected into the floating gate 1102 to the source region 1105.
However, in the above cell structure, as shown in FIG. 2, when a high voltage is applied to a source region in an erase operation, band bending occurs in a surface of a source region 1203 at a portion which overlaps a floating gate 1202. As a result, band to band tunneling occurs, and electrons 1205 and holes 1206 are generated in a depletion layer 1204. The electrons 1205 and the holes 1206 generated by the band-to-band tunneling are accelerated by a reverse biasing voltage between a source region 1201 and a substrate 1208 and cause impact ionization, thereby generating a number of carriers in the source region 1201. The carriers thus generated flow as a current between the source region 1201 and the substrate 1208. If the impurity concentration of the source region is uniform, when a gate-source voltage VGS is maintained on a level required for the erase operation as shown in FIG. 3, the band-to-band tunneling current greatly depends on the potential difference between the source region and the substrate, in a case where the potential difference is smaller than 3 V. The potential difference between the source region and the substrate does not greatly depend on the structure, such as the concentration profile of the diffusion layer of the source region, but is considered to be determined by a silicon band gap. This matter is reported by, for example, K. T. San et al. (IEEE Transaction on Electron Device, vol. 42, No. 1, page 150, 1995).
Part of the holes 1206 generated by the band to band tunneling are injected into an oxide film 1207 in an erase operation. After program erase cycles, a very small leakage current flows in the oxide film even in a low electric field. In this case, if the memory device is left for a long time, various problems may occur, e.g., lost of the electrons in the floating gate, resulting in a malfunction of the memory device.
One of the methods for reducing the band-to-band tunneling current under the constant voltage applied across the floating gate and the source region is to attenuate a lateral field in an erase operation by means of a double diffused junction structure, in which the source region is constituted by an N-type low concentration impurity region and an N-type high concentration impurity region, as shown in FIG. 4. This method, however, is disadvantageous in that, since the source region is deep, the gate length of the cell transistor cannot be scaled down.
Another method for reducing the band-to-band tunneling current is to set the source voltage to, for example, 2 V, utilizing the characteristic that the band-to-band tunneling current is markedly reduced, as shown in FIG. 3, in a region where the source-substrate voltage is smaller than 2.5 V. However, if the source voltage is simply lowered, a high negative voltage must be applied to the control gate in order to maintain a practically sufficient erasing speed. For example, if the source voltage is 2 V, a negative voltage of -13 V must be applied to the control gate. In general, a negative voltage applied to a gate is generated by a booster circuit in a chip. Therefore, to increase the voltage to be applied to the gate, the space occupied by the booster circuit must inevitably be increased. In addition, the transistor for driving the control gate must have a high breakdown voltage. Since the gate oxide film must be accordingly thick, the performance of the transistor is lowered, resulting in an increase in access time. Although the case of extracting electrons from the floating gate into the source region has been described above, the same problems occur in a case of extracting electrons into the drain region.
Besides the method of extracting electrons into the diffusion layer of the source or drain region, electrons can be extracted into the overall surface region of the channel. FIG. 5 shows a structure for extracting electrons into the surface region of a channel. A cell region is formed in a P-type impurity region 1402 formed in an N-type silicon substrate 1401. A high voltage is applied across the control gate 1405 and each of the N-type silicon substrate 1401, the P-type impurity region 1402, and source and drain regions 1403 and 1404, thereby extracting electrons into the overall surface region of the channel. The above method is disclosed by T. Jinbo et al. (ISSCC Digest of Technical Papers, page 155, 1992). In this method, however, as reported by H. Kume et al., since electrons pass through the overall surface region of the channel, an interface state is generated in an oxide film adjacent to the channel region by repeated program erase cycles. Therefore, the current drivability of the transistor is lowered (Symp. on VLSI Technology, Dig. of Technical Papers, Page 77, 1991).
As has been described above, the conventional Flash EPROM has a drawback that an excessive band-to-band tunneling current flows in an erase operation, and to suppress the band-to-band tunneling current, the performance of a memory cell is degraded.